Integrated circuit memory includes dynamic random access memory (DRAM) and static random access memory (SRAM). DRAM cells provide good memory density, but are relatively slow. A conventional DRAM cell includes an access transistor integrated with a relatively complex capacitor structure. A goal for a conventional DRAM cell design is to achieve a cell density of 8 F2, where F is the minimum printable feature size. SRAM cells are faster but require more area than DRAM cells. A conventional SRAM cell includes four or six transistors with a cell density ranging from 50 F2 to 100 F2. A SRAM cell design goal is high performance, but the larger area associated with four-transistor and six-transistor memory cells limits the use of SRAM devices.
Negative Differential Resistance (NDR) devices have been used to reduce the number of elements per memory cell. However, NDR devices tend to suffer from problems such as high standby power consumption, high operating voltages, low speeds and complicated fabrication processes.
F. Nemati and J. D. Plummer have disclosed a two-device thyristor-based SRAM cell (referred to as TRAM) that includes an access transistor and a gate-assisted, vertical thyristor. The disclosed vertical p+/n/p/n+ thyristor is operated in a gate-enhanced switching mode to provide the memory cell with SRAM-like performance and DRAM-like density. The performance of the TRAM cell depends on the turn-off characteristics of the vertical thyristor, and the turn-off characteristics depend on the stored charge and carrier transit time in the p region of the p+/n/p/n+ thyristor. The turn-off characteristics for the vertical thyristor is improved from milliseconds to five nanoseconds by reverse biasing the thyristor for a write-zero operation and by using a gate to assist with turn-off switching of the thyristor by discharging the stored charge. Known memory cells with gated thyristors use a second word line on a separate level to gate the thyristor, and further use a separate anode contact (e.g. Vref node) for turning on the thyristor, both of which increases the complexity of the fabrication process and adversely affects the yield and the density of the memory cell.
Capacitor-less single transistor DRAM and associated gain cells have been proposed where the floating body charge defines the memory state and the channel conductance of the transistor. The change in body potential and the excess carrier lifetime in the floating body limits the memory state stability. A single transistor vertical gain cell uses body capacitor plates to enhance the storage capacity (US 20040042256). A non-volatile one-transistor SOI memory device stores charge in a trapping layer in the floating body to provide non-volatility of the memory states (US 20040041208).
It is desirable to develop memory devices that provide DRAM-like density with SRAM-like performance while eliminating elements from the memory cell design, such as capacitors, second word lines and separate thyristor anode contacts, that complicate the process for fabricating memory cells.